The present disclosure relates to a power supply circuit, and more specifically to a power supply circuit that can reset gate lines in a display panel, and to a corresponding driving method of this display panel.
When a display device enters a power-off status, residual electric charges remain in pixels of the display panel after power-off, and these residual electric charges stay in the pixels until the next power on, resulting in an abnormal display (flickering) when the display device powers on again. In order to address this problem, a conventional power supply circuit outputs a reset signal to a gate drive circuit in the display device before an operating voltage drops to 0 V, such that the gate drive circuit simultaneously drives all gate lines in the display panel based on the reset signal, so that the residual electric charges in all pixels are released.
FIG. 1 is a block diagram of a conventional display device. As shown in FIG. 1, a display device 100 includes a power supply circuit 101, a gate drive circuit 102, and a display panel 103. The power supply circuit 101 receives an operating voltage VCC, and accordingly outputs a high voltage level VGH and a low voltage level VGL (the low voltage level is lower than 0 V) to the gate drive circuit 102, such that the gate drive circuit 102 can generate a gate pulse based on the high voltage level VGH and the low voltage level VGL. When the display device 100 powers off, the power supply circuit 101 outputs a reset signal XON to the gate drive circuit 102 before the operating voltage VCC drops to 0 V, in order to control the gate drive circuit 102 to generate multiple gate pulses through the operation of an internal shift register SR and a level shifter LS, and thus simultaneously driving gate lines G1-Gn, and further releasing residual electric charges in all pixels.
However, when the display device 100 powers off, both the potentials of the operating voltage VCC and the high voltage level VGH drop to 0 V, and the low voltage level VGL restores from a negative voltage to 0 V. When the operating voltage VCC drops below a critical level, the level shifter LS in the gate drive circuit 102 is unable to operate normally, the gate drive circuit 102 is unable to output sufficient gate pulses in response to the reset signal XON to simultaneously drive the gate lines G1-Gn, and thus the residual electric charges in each pixel of the display panel 103 are not released as expected.